Timing circuitry in a drum storage computer system



March 19, 1968 D. T. BEST ET AL 3,374,462

TIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM Original Filed Aug.15. 1956 15 Sheets-$heet 1 B REszsTER 52 ARITHMETIC SCANNER CONTROL 54so 62 s4 ACCUMULATOR ADDRESS KEYBOARD U PUT AND CIRCUITS LOOP SELECTORPRINTER L GENERAL CONTROL 70 TIMING PROGRAM ST T CIRCUITS CONTROLSELECTOR 72 PINBOARD F I g 2 INVENTORS.

I DONALD T. BEST 46 JOHN R. VAN ANDEL ATTORNEY March 19, 1968 15551 ETAL TIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM 15 Sheets-Sheet 4Original Filed Aug. 15. 1956 mm l Om mm I Om mh l ON mm I Ow mm I On mvi Ow mm I On mm I ON 9 l O m0 I O0 mwwmmmom llllllllll mm m Mn N wxu nt.mwkmawm OZUEO? N mxoqmk 02:2; .0

INVENTORS. DONALD T BEST JOHN R. VAN ANDEL ATTORNEY March 19, 1968 1",BEST ET AL.

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INVENTORS DONALD T. BEST BY JOHN R VAN ANDEL March 19, 1968 BEST ET ALTIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM 15 Sheets-Sheet 6Original Filed Aug. 15, 1956 $1; mwoz n Maia 911 L0 37: 51 2 x E0252 kM211 l 1 1 5:52 Cm wza zm S23 823 A H E $985 2; M b Q A $2 9 $2 9INVENTORS DONALD 1'. BEST W B JOHN R VAN ANDEL ATTORNEY March 19, 19681- ET AL 3,374,462

TIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM Original Filed Aug.15, 1956 15 Sheets-Sheet '2' 1311 SEC MQQIVLFIED VIEWS CLFRAW T'MINGPULES BLISEC' T 9 O I 2 3 4 5 A6 A? A? [\9 f \O f \5 I300 RAW T"PULSESPER DRUM REV 65L] SEC (30H SEC I DE (ma 1 (E) (mmm [3O PAIRS PER DRUMREV WBC EL m (ONE PAIR oFws PULSES LIKE THIS) I2 PULSES PER DRUM REVTYPES 9f LQERIVEQ PLJLSES TRIGGER PULSES(I300+,I300u,2600+vu PER REV) +1-|u sEc +H IL ILIL H H FEFEIEH H H H +H4-IUSEC HEH MIEH WWFEH H H H+H4-IUSEC Wu 9900il223344556677889900l DRUM WRITING PULSESUSOOPERREV.)+H4-L5LJSEC w e no 2 3 4 5 H6 7 8 no H BIT PULSES (i300 PER REV.) +1y+2u SEC H H FU n mwn n wn n n m +H+2LJSEC U FL FL H'FEWWWH H H H HSAMPLER DR cRDPPER PULSES(26OO PER REV.) +q zusEcTVU99OO1|223344556677889 001 DIGIT PULSES (l3OD l30E PER REV) P-ZUSECD=DET+|6E ITI H+2USEC woRD PULSES (IO PER REV) W=wBC-D 14-2 u SEC INDEXPULSES (IBJC PER REV) -2U SEC B=WBO-DE-T |2u sEc c=wBc--DEu L INVENTORS.

DONALD T, BEST JOHN R VAN ANDEL F I g. 8 BY ATTORNEY March 19, 1968 1'BEST ET AL 3,374,462

TIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM Original Filed Aug.15, 1956 15 Sheets-Sheet 5 TUNED TUNED OVERDRIVEN AMPLIFIER AMPLIFIERAMPLIFIER SHAPING SINE WAVE OUTPUT F lg. 10

INVENTORS, DONALD 1'. BEST JOHN R. VAN ANDEL ATTORNEY March 19, 19685557 ET AL 3,374,462

TIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM Original Filed Aug.15, 1956 15 Sheets-Sheet Q +9OV +2|OV K L M T T 2.20 56K; 5Mh z nssfi/l3s YO a: 1:: I36

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DONALD T. BEST BY JOHN R. VAN ANDEL ATTORNEY March 19, 1968 T ET AL3,374,462

TIMING cmcumm IN A DRUM STORAGE COMPUTER SYSTEM Original Filed Aug. 15,1956 15 Sheets-Sheet I 1 +2Iov I500 I58 H F lg. 15 0 I I I INPUT I A A HA OUTPUT DIFFERENTIATING LINEAR OVERDRIVEN AMPLIFIER AMPLIFIER AMPLIFIERSHAPER F lg. [5b

INVENTORS.

DONALD T BEST JOHN R. VAN ANDEL ATTORNEY March 19, 1968 T ET AL3,374,462

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INVENTORS, DONALD T. BEST JOHN R. VAN ANDEL ATTORNEY March 19, 1968 BESTET AL TIMING CIRCUITRY IN A DRUM STORAGE COMPUTER SYSTEM 15 Sheets-Sheet15 Original Filed Aug. 15, 1956 ONT Om O O o o o o O T W Y T EA E m B NW VTA O mo w M A QOOJ 1065mm 3 dzmia nm mm w W m m w w w mm om mo-ow m wm m mmljuiq March 19, 1968 BEST ET AL TIMING CIRCUITRY IN A DRUM STORAGECOMPUTER SYSTEM 15 Sheets-Sheet 14 Original Filed Aug. 15, 1956 wow macmac vac A 5 N 9% 25016 L mzummbwmvmm o m mm:

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m o whim 4% m v mbpw mm WEE; nqwm Duo INVENTORS DONALD T BEST mom JOHNR. VAN ANDEL O w: w mw 325552 5Q mom ATTORNEY United States PatentOfifice 3,374,462 Patented Mar. 19, 1968 3,374,462 TIMING CIRCUITRY IN ADRUM STORAGE COMPUTER SYSTEM Donald T. Best, Plymouth Meeting, Pa., andJohn R. Van Andel, Dcarhom, Mich assignors to Burroughs Corporation,Detroit, Mich., a corporation of Michigan Original application Aug. 15,1956, Ser. No. 604,153, now Patent No. 3,144,549, dated Aug. 11, 1964.Divided and this application July 24, 1963, Ser. No. 297,348 Claimspriority, application Great Britain, Mar. 2, 1956, 6,693/56 18 Claims.(Cl. 340-1725) This application is divided from copending applicationSer. No. 604,153, filed Aug. 15, 1956, by George G. Hoberg et al., nowUnited States Patent No. 3,144,549, which in turn is a division ofapplication Ser. No. 492,062, now United States Patent No. 3,053,449.

This invention relates to electronic digital computers and moreparticularly to data storage and information location devices operablein general-purpose computers having a plurality of automaticallysequenced program steps adapted to enable the computer to perform manydifferent types of programmed operations.

In general, electronic computers have been difficult to operate andhighly skilled and specialized operators have been necessary for settingup programs to enable the computer to solve the desired problems. Thesecomputers have been highly proficient in solving the problems afterbeing properly programmed. However, the programming technique requiredin prior art general-purpose computers has necessitated extensivetraining courses, and has resulted in establishment of a few keypersonnel upon which the operation of the machine depends. Not only hasthis caused personnel procurement problems, but it reduces the duties ofpersons charged with the solution of problems to the mechanical routineof gathering data. This results in losing the feel for the problem andits solution and the ability to sense whether the solution is properbecause all contact by the problem originator with the procedures bywhich the problem is carried out is broken. Even should these persons dothe programming they may not understand the procedures followed in theproblem solution because they have to think in terms of coded arithmeticnotation rather than in terms of the decimal notation with which theyare familiar. In the solution of scientific and business problems,scientists and the businessmen have not favorably reacted toward a lossin feeling for finding solutions when using electronic computers, exceptin those cases where a time schedule bottleneck overrides thedesirability for maintaining contact with the procedures by which theproblem is solved.

It is, therefore, an object of this invention to produce an electroniccomputer which enables an operator to maintain touch with the manner ofsolving a problem and yet in which the more routine of arithmetic orrecording is done automatically at high speed by the electroniccomputer.

Another object of the invention is to produce a simply programmedelectronic computer capable of operation by unskilled personnel anddesigned for operation directly in decimal notation although features ofthe invention are not limited to such notation.

Accordingly, the electronic computer afforded by the present inventionprovides simplicity of operation and flexibility of control withprovisions for manual operator intervention at any stage of theprogrammed problem. Thus, the operator may view partial results andthereafter cause the computation to proceed in accordance withintelligible judgment which cannot be done readily in the machineitself. The computer is designed to aid the operator in understandingthe nature and the status of the problem as it progresses through thevarious automade or optional manual control steps. Visual aids areafforded showing the condition of the machine during the differentoperational steps. In addition, the machine is provided with visuallypinned program instructions to enable the operator at all times torecognize the program in progress. The pinboard also permits flexibilityin the choice of programs and rapid changing of the computer from oneprogram to another without danger of improper connections because ofwiring complexity.

Prior art general-purpose computers have been designed which areextremely high in cost and comprise excessive amounts of equipment whichutilize large amounts of power in operation. Such machines have beenavailable to only those relatively few users who have control ofunlimited funds for acquiring and operating such machines.

Accordingly, another object of the present invention is to provide aflexible small size general-purpose digital computing machine.

A further object is to provide such an electronic digital computer whichis both low in initial cost and in operating cost.

In a computer of the type described, information must be stored forready access to the computer when required. One form of a suitablememory is cyclically movable magnetic storage means such as a magneticdrum. In providing such storage means, many problems are encountered inaccurately reading and writing information in specified memorylocations. It is usual to provide timing pulses directly recorded uponone drum channel or track for identifying cell locations. However,certain noise signals may be induced upon the timing track during use,and accordingly erroneous operation may be encountered.

Timing signals of several different types may be recorded in separatememory channels, to thereby provide the necessary operation of differentcomputer control circuits. It becomes cumbersome and expensive, however,to have separate tracks for all the various timing signals, and thevarious timing signals must be recorded upon the movable memory medium,to assure the exact timing necessary for locating stored information.

Different recorded information records must be located with computerinstructions and control circuits by utilizing the recorded timingsignals, and the address location circuits must be operated in propersequence with other computer functions to properly time the presentationof information with the corresponding data processing operations.Control circuits for locating signals and the corresponding instructionsheretofore have been more complex than feasible for use in low costcomputers with limited program facilities. Thus, it becomes necessary toprovide more clficient use of programming facilities in locatingaddresses of recorded information records.

Accordingly the present invention overcomes these difilClllllES andaffords improved memory systems operable in low cost computers toaccurately locate and process stored information.

An object of the invention therefore is to provide magnetic memorysystems which are non-responsive to noise signals encountered in timingsignal channels.

Another object of the invention is to provide a plurality of separablerecorded timing signals upon the same track of a cyclically movablememory medium together with simplified control circuits fordistinguishing the separate signals.

A further object of the invention is to provide simplified and flexiblememory address locating circuits operable in computers having a limitednumber of program facilities.

in accordance with this invention, therefore, there is provided a cyclicmagnetic memory device having recorded thereupon timing control signalsand selectively alterable data. Processing circuits are provided forreproducing the recorded timing signals in accurate timing relationshipwithout interference by interspersed noise signals which might otherwiseinterefere with computer operation. This is accomplished by convertingrecorded timing signals to sine wave signals in tuned circuit amplifierto thereby exclude signal components non-periodic at the fundamentaltiming pulse presentation frequency. Furthermore, eflicientamplification is realized by employing the greater amplifier gain of atuned circuit. Fundamental circuit timing is thereby controlled only bythe periodic presentation frequency of actually recorded timing signals.Several sets of auxiliary timing control signals are recorded in atleast one separate timing track for use with the fundamental timingsignals to reproduce several separable sets of further computer timingcontrol signals.

Address locating circuits are provided operable from different ones ofthe computer timing control signals. These address locating circuits areresponsive to computer programming signals in such a way that fewprogram steps are required for locating several memory addresslocations. Thus, scanning switches are provided for optional control ofmemory location, and these scanning switches are connected for operationby certain special computer instructions. Thereby, a sequence of memorylocations may be selected by a single memory address instruction coupledwith a special scanning switch instruc tion to thereby reduce the numberof programming steps required without processing address instructionsthrough the computer arithmetic section for modification and therebygreatly increasing the required control and data processing cihcuits.

A more detailed description of the electronic computer, organization andmode of operation together with the accompanying electronic circuits andoperational features of advantage of the data storage circuits aredescribed hereinafter with reference to the accompanying drawings,wherein:

FIG. 1 is a perspective view of the electronic computer console;

FIG. 2 is a generalized block diagram of the several functional computersections;

FIGS. 3, 3a and 3b show in more detailed block diagram form therelationship of different functional units of the computer;

FIG. 4 is a diagrammatic view of a magnetic drum mem my device of thecomputer;

FIG. 5 is a plan view of a pinboard used for programming the computer;

FIG. 6 is a plan view of the computer manual control panel;

FIG. 7 is a logical block diagram of signal processing circuits forstored timing and data information;

FIG. 8 is a waveform diagram of timing pulses used in the computer forscheduling operation;

FIGS. 9 through 16 are detailed diagrams of data processing circuitsshown in FIG. 7;

FIGS. 17 through 19 are schematic diagrams of memory reading and writingcircuits; and

FIG. 20 is a diagrammatic representation of address selection circuits.

In order to facilitate comparison of circuits throughout the computer,like elements are given similar reference characters. In the detaileddescription of the computer system the reference characters are referredto the figures in which they are shown by a prefix numeral, and likewisecross reference is made from reference characters of one figure toanother, wherever convenient. Wherever possible, to simplify notation,alphabetical reference characters are used on terminals and localizedelements. In view of the complexity of the system, descriptive legendsare used in connection with some of the figures to enable correspondingcircuitry to be compared without detailed reference to thespecification.

In FIG. 1 is shown a perspective view of the desk-size computer console.A ventilated rear cabinet housing section 1-40 contains the electroniccomputer circuits which are generally mounted in standardized plug-incircuit units. The circuit housing section 1-40 pivots open for readyaccess in servicing the interior elements, and is further provided withremovable cover sections 1-41 and 1-42 for access to circuits exposed atthe rear of the cabinet.

The desk section 1-43, in general, houses the power supply and memoryunits, which are accessible through opposite end panels 1-44. On thedesk top is affixed an input-output unit 1-45 herein identified as akeyboardprinter and a visible control panel 1-46 employing removablepins into which is programmed the automatic instruction sequence to beperformed by the computer. A pivoted compartment drawer 1-47 houses amanual control panel 1-48, which may be used for setting up operationconditions in the computer and for modifying the automatic instructionsequence.

The block diagram circuit of, FIG. 2 illustrates the overall operationalrelationship of different computer units. The computer units are shownin functional rather than physical relationship. For example, the memoryunit 2-50 comprises several tracks of a rotating magnetic disc or drum,while the B register 2-52 and accumulator loop 2-54 each comprisefurther single tracks on the same rotating storage device. The timingcircuits 2-56 may be also actuated from timing signals synchronized withfurther tracks upon the rotating storage device. Input-output circuits2-62 are provided to assure that the electronic computer timing circuits2-56 and the keyboard and printer 45, which has an independent operatingcycle, are synchronously sensed. In this way separate buffer memorydevices are eliminated. The keyboard and printer 45 with its internaloperation cycle includes further transition timing cam means notassociated with the block 2-56 for enabling the transfer of informationbetween the keyboard and printer unit 45 and the synchronously operatedcomputer circuits. In this respect the more detailed presentation ofFIGS. 30 and 3b shows that the timing cam produces rack stop signals atsection 3-49 which under control of the multivibrator 3-76 serves totime the firing of the rack stop thyratrons 3-77 in response to signalsat the accumulator 3-59 or read-write circuits 3-55 when accompanied bythe readout instruction.

All arithmetic operations are under control of circuits within thearithmetic control unit 2-60 or the general control unit 2-70, and alldata transfers through the inputoutput circuits 2-62 and addressselector unit 2-64 make use of the accumulator loop 22-54, whichcomprises a regeneratively controlled data track upon the rotatingstorage device. The arithmetic operations are scheduled by a program setup in the pinboard 46. Each program sequence may be automaticallyscanned step by step with the program control circuits 2-68. Thearithmetic control unit 2-60 and B register 2-52 are used primarily formultiplication and division operations, and the general control circuits2-70 are used to schedule each of the several operations for which thecomputer is designed. The general control circuits operate from ascheduled selection of eight different computer states set up by thestate selector unit 2-72.

The scanner unit 2-74 counts the decimal digits of a numerical word. Itis used to enable the keyboard digit to be read into the accumulatorsynchronously, and also is used in multiplication and division to choosethe proper multiplier and quotient digits respectively. Thus, the inputkeyboard-set signal may be statically held until the final use has beenmade of an input word and therefore internal storage registers areunnecessary for the input word.

A more detailed block diagram organization of the computer is shown inFIGS. 30 and 3b. The heavy lines of FIG. 31: indicate informationprocessing paths, whereas the lighter lines indicate control signalpaths. As with FIG. 2, each of the block units of FIG. 3 willhereinafter be described in detail and will be identified in differentfigures where feasible with similar reference characters. The computerdescribed in FIGS. 3a and 312 has functional block units assembled in acomputer circuit typifying the details of a typical model of a computerconstructed in accordance with the invention. Thus, it is readily seenthat the typical details described in connection with some of the unitsmay readily be modified by those skilled in the art without departingfrom the spirit or scope of the present invention. Certain such specificdepartures such as the amount of storage and number of instructionsavailable in different computer models will be later described.

In the rotating magnetic memory unit 3-51, each data word has twelvedecimal digits plus sign and is stored in serial form so that the signmay be read first and then the least significant digit, etc., as shownin FIG. 19. Each digit is stored in pulse-count form with memory bitcells allocated for each digit. The tenth spacer cell located betweentwo successive digits is not used for bit storage since the digits fromzero through nine need only nine of the ten available bits.

A typical rotating memory device is the magnetic drum 51, which isdiagrammatically shown with associated memory tracks in FlG. 4. Thismagnetic drum when rotated at about 3,600 rpm. provides scanning timefor one track revolution of about seventeen milliseconds. Thus, theaccess time for one of the ten words storcd in equidistant peripheralarcs or sectors around each track is about one and seven-tenthsmilliseconds.

The data memory comprises ten drum memory tracks each storing ten wordsfor a total of one hundred word memory. Each track is given an addresscomprising a tens decimal digit (10) and each word sector is given anaddress comprising a units decimal digit (10) so that the entire onehundred word memory address may be signified by a decimal number fromzero to ninety-nine. Each data track has a separate magnetic read-writehead which is selected by the head switching circuits 3-53 under controlof a programmed address track selector digit. The recorded druminformation, which is read, is then passed on to the read and writecircuits 3-55 for amplification and processing. Likewise, computerinformation to be Written on the memory is passed through the read andwrite circuits 3-55.

The drum. in addition to the memory tracks, is provided with two workingregister tracks. The B register track 2-52 has one word repeated tentimes for use as the multiplicand or divisor in the multiplication anddivision operations. Thus, each multiplier word has a read time of oneand seventcnths milliseconds, and reading from the drum may start at theclosest word position. The A register track 3-57 is a circulating oneword track, which also provides a read time of one and seven-tenthsmilliseconds from the start of the word. This track 3-57 is connected inthe accumulator loop to serve as an accumulator register.

Three separate timing tracks are provided in the timing storage memorysections 3-78 for the hit, word. digit and rotation timing or flagpulses. There are 1,300 hit timing pulses on the basic track thusserving, at 3,690 r.p.m., to produce a '78 kilocycle basic computeroperating frequency. This provides for ten words of twelve dscimaldigits plus sign in the pulse-count notation on each track. The WBCtrack produces ten word pulses and one each It and C rotation or flagpulses, which are distinguished in the manner shown in the timing chartexplained hereinafter in connection with FIG. 8. The B pulse coincidesin time with the T pulses on the basic timing track and the C pulse isspaced between two T pulses for presentation at U time one-half drumrevolution from the B pulse. It may be noted in FIG. 8 that the timeaxis for the pulses derived from the VVBC track is broken to show the Cpulse which occurs half a drum revolution, or 650 bit timing T pulses,later than the 13 pulse. It will appear from the above that the C pulsethus occurs five words later than the B pulse, each word having 13decimal digits of ten bits each. The DE timing track provides digitpulse pairs for each drum rotation, Thus another I pulse occurssimultaneously with a D pulse shortly before the C pulse occurs. To makethe C pulse come at U time instead of T time. the C pulse, of course,has to occur slightly longer after its W pulse than did the B pulseafter its W pulse. This additional delay of the C pulse also preventscoincidence of the C pulse with an E pulse, as is necessitated by helogical operation for isolating the C pulse, represented at the extremelower right corner of Fit). 7. The same logical operation is summarizedin the graph on the right side of the bottom line of FIG. 8. where thetime axis also is broken and does not coincide with most of the othergraphs on that figure but does coincide with the timing of the C pulseshown on the WBC track, mentioned above. The timing signals are passedfrom the timing track section 3-78 through the read and write circuits3-55 to the timing circuits 3-56 which are used to synchronizeoperations by gating signals at local circuit positions throughout thecomputer.

For translation of data between the rotating memory 3-51 and othercomputer units, all data is processed through the read and writecircuits 3-55 and the accumulator 3-59. The accumulator principallycomprises a serial pulse-count adder circuit, which is coupled in a loopcircuit with the A register memory track 3-57 through the shiftingcircuits 3-61 and writing section 3-453. Data may al o be transferredbetween the memory unit 3-51 and the keyboard and printer 45 by way ofthe accumulator 3-59 and writing section 3-63.

The keyboard and printer 45 may be incorporated in a standard businessmachine of the type described in the United States Patent No. 2,629,549,issued Feb. 24, 1953, to T. M. Butler for Automatic Function ControlMechanism for Accounting Machines. This machine provides a selectableprinted format control from a semi-ganged high speed printer by meansof. a mechanically programmed control tray in the machine. Thus, aprinted page may be produced directly from the electronic computercircuits in any desired type of format. Each printed output word willhave twelve decimal digits plus sign and the keyboard has eleven inputdigits. The read-out conversion from the business machine keyboard to anelectronic circuit is accomplished by readout switches 3-65 as describedand claimed in the application for United States patent for Switchlvlechanism, by William Ward Deighton, filed Jan. 6, 1955, Ser No.488,366, now abandoned, and assigned to the same assignce as the presentapplication. The read in section 3-67 transfers data from electroniccomputer circuits to the printer by means of solenoids 3-69 which serveto stop the business machine printing racks. in u desired position inthe mar-oer described in United States Patent 2.822.752, issued Feb. ll,1958, to R. S. Bradshaw et at, for "Dilicrential Tyre Setting andResetting Means. and assigned to the same assignce as the presentapplication. Since the business machine operates on its own internalread-out and print cycle which is asynchronous with the operation of therotating magnetic memory in the computer, the control cam and tap-petsolenoid section 3-71 is provided for transition timing of the keyboardand printer operations with the function thyratron circuits 3-80 and thestate counter 3-82. shown in FIG. 31]. This control section 3-71 isdescribed in the United States Patent No. 2,836,- 355, issued May 27,1953, to O. W. Banik et al., for Remote Function Control Systcnt." andassigned to the some assignee as the present appiication.

Data is transferred from the keyboard through readout switches 3-65 andby way of the counter VI input circuits 3-73 and the sector addresscounter 3-75 to the accumulator 3-59. Conversely. data is transferredfrom the computer to the printer from the writing section 3-63 throughthe rack stop thyratron circuits 3-77 and 7 the rack stop solenoids3-69. All of the data processing units and paths described may be placedunder control of either automatic or manual computer sections 3-46 or3-48 by prescribed instructions.

The timing circuits 56 of FIG. 3a are used to reform and gate signalsthroughout the computer to ensure opera-- tion upon the proper data andto maintain synchronism in the computer.

All of the arithmetic operations are timed by means of signals derivedfrom stored timing signals in the memory section 3-78 with circuitslocated in the read section 3-55 and processed in the timing circuitsection 56 of FIG. 3. These timing circuits are shown in more detailedblock diagram form in FIG. 7. The corresponding Waveforms areillustrated in FIG. 8, and detailed schematic circuits are found inFIGS. 9 through 16. The block diagram circuits of FIG. 7 are discussedtogether with timing pulse characteristics of both the raw recordedpulses and those timing pulses derived therefrom as in dicated by thewaveforms of FIG. 8.

The basic timing track has 1,300 raw timing pulses T spaced at thirteenmicrosecond intervals which are used to derive pulses for synchronousoperation of the computer at bit frequencies of either 78,000 or 156,000cycles per second. The raw timing pulses T are used in the basic timingsection 7-130 for deriving a series of shaped pulses r, u, tvu, T, U,TvU, and w. The timing and widths of these pulses, together with anindication of the timing of the decimal pulse count notation in thecomputer system are seen in the waveforms of FIG. 8. From thecorresponding letter notation at the output leads of the basic timingsection 7-130 each timing signal may be traced back to the basic timingtrack through the processing circuits, which may be constructed as shownschematically in detail in FIGS. 9 through 16.

Thus, in FIG. 7, the raw basic timing pulses T are fed through the twostage tuned amplifier circuit 10-134 of FIG. 10 to produce a sine waveoutput signal at terminal C. The block notation of FIGS. 10, 12 and 14may be compared with that of the basic timing processing circuits 130 ofFIG. 7 to indicate the manner in which the circuits of FIGS. 9, 11 and13 are employed. Shaping of the sine wave signal at terminal C isperformed by overdriving a biased triode amplifier 9-132 in a circuitproviding lowered plate potential from the +90 volt supply. Thiseffectively converts the sine wave output signal of the intermediatetuned amplifier 9-134 to a shaped wave at the output terminal Y of theoverdriven shaping amplifier 9-132, from which is derived in furthercircuits the one microsecond wide I and u pulses of FIG. 8.

The shaped wave at terminal Y is further processed in the circuits ofFIG. 11, as shown diagrammatically in FIG. 7 and FIG. 12. Thus, thepentode amplifier tube 12-136 serves as a further peaking circuit toproduce at the output terminal K the t timing pulse. The peaking is donein a damped resonant pulse forming circuit 11-138.

To form the u timing pulse, an inverter circuit comprising the triodeamplifier 11-140 is used to produce an input signal at lead 11-142 to afurther pentode peaking circuit 11-136 to produce at the output terminalL the shaped u timing waveform. Thus, by utilizing the reverse halfcycle of the available shaped sine wave, the t and u clock pulses arecaused to be interspersed with each other, as shown in FIG. 8.

The w drum writing signal also is derived from the sine wave signal atterminal C. The signal at the input circuit terminal R of the overdrivenamplifier 12-132 in the w signal processing circuit is advanced by meansof a suitable phase advancing circuit, such as 13-146, which causes thew timing pulse to have a leading edge starting one-half of a microsecondbefore the corresponding 1' pulses. The damped resonant pulse formingcircuit is tuned to produce a one and one-half microsecond pulse. Thus,the w pulses last for a duration of one and one-half microsecond, andare therefore suitable for actuating circuits for writing upon themagnetic drum. In the computer system these wider pulses permit thestorage of more energy. The peaker stage 12-136 further shapes the wwaveform to produce output pulses at terminal M.

The further two microsecond wide clock pulses T and U are derived incircuits of the type shown in FIGS. 13 and 14 from the sine waveproduced at the input terminal C. A cathode follower circuit 14-144couples the sine wave signal to two separate processing channels for therespective clock pulses T and U. An inverter circuit 13-140 serves tointersperse the U pulses with the T pulses by utilizing a different halfcycle of the sine wave input signal. By means of the interspersed phaseadvancing circuits 13-146, the sine Wave signal is caused to trigger offthe overdriven amplifiers 13-132 soon enough to cause the T and U pulsesto be derived for two microseconds of which the latter microsecondcorresponds with the 1' and u trigger pulses. The phase advancingcircuits comprise simply the input R-C coupling circuit to theoverdriven amplifiers 13-132 comprising the 220 micromicrofaradcapacitor 13-146. The pulses are finally shaped in the peaker circuits13-136 to produce at the respective output terminals X and T the shapedT and U pulses.

Some of those circuits described in connection with the basic timingprocessing circuits 7-130 are likewise used for processing the othertiming track and data track signals in sections 7-150, 7-152 and 7-178of FIG. 7. A differentiating amplifier 15-148 is used in the memoryreading stage of the amplifier circuits in reading sections 7-152 and7-178 of the type shown in detail in FIG. 15. Thus, the pentode tubepresents a high resistance and the choke 154 has a low inductance sothat the output pulses are differentiated as applied to the cascadecoupled linear amplifier circuit 15-158. The pulses are then shaped inthe overdriven amplifier 132 to produce output signals at the terminalI. The differentiating amplifier provides a maximum output incoincidence with the maximum flux density of the memory track.

These shaped signals are further processed through the pulse amplifiercircuit 16-160 (FIG. 16a) as are the signals derived from the basictiming track as indicated in the pulse amplifier circuit portion 7-161.The amplifier circuit of FIG. 16 is shown in universal form so that itmay be utilized throughout the computer wherever pulse amplification isnecessary. This is particularly true in some of the diode logiccircuits. As is well known, after a pulse has passed through severaldiode logic stages, inherent circuit delays cause the pulse to be spreadout and misshaped. Thus, fresh timing of the input signals with anappropriate clock pulse is accomplished by means of the diode "andcircuit 16-163. This and" circuit is a conventional circuit comprisingtwo diodes which serves as the input circut for the 6AN5 pulse amplifiertube 16-165 coupled by resistor 164 to a source of positive potentialv.) and is supplied with a source of positive input pulses at either oneof the two diode cathode input terminals R and S. Thus, both diodes haveto be cut off in order to produce a positive output pulse at the controlgrid of the pulse amplifier tube 16-165. Throughout the followingspecification and circuit embodiments, gates constructed schematicallyas those gates 16-163 are shown in the logical form of HG. 16a. Thus,the and circuits 163 of FIG. 7 may be of this type. It is to berecognized, of course, that more than two input signals can be affordedby likewise connecting more diodes and input terminals to the resistor16-164 in the same sense. Thus, the coinci dence of all input signalpulses will produce a single output signal pulse.

The coincident pulses are simplified by the tube 16-165 and are coupledto the pulse transformer 16-167. In order to provide standard pulses foruse in inhibiting as well other logic functions throughout the computer,two secondary windings 16-169 and 16-170 are used respectively forproducing positive and negative output pulses.

All the pulses produced are of an amplitude of about twelve to fourteenvolts, since this potential produces the highest back resistance in thecrystal diodes used for logic and clamping purposes.

In each of the secondary windings 16-169 and 16-170, :1 2 voltdifferential is provided across the diode circuits in order to produce athreshold for eliminating small transient noise signals. The outputsignals are respectively clamped at 12 volts and ground potential. Alsoin order to produce high quality pulses without transient ringing, theresistors 16-171 and 16-172 serve together with the clamping diodes16-173 and 16-174 connected in series therewith to critically damp thesecondary windings for a single half cycle of oscillation. Thus, withthe described circuit the input waveforms are accurately retimed by theinput and circuit 16-163 and are produced in amplified form by the pulseamplifier circuit 16-160 to produce shaped output pulses at the pulsetransformer 16-167.

The various combinations of timing pulses which are necessary atdifferent stages of the computer for proper operation are derived in theand circuits of the processing section 7-176 of FIG. 7. Since digitalinformation is handled throughout the computer system, the data tracksderive similar shaped pulses in the power amplifier circuits 16-160 ofthe data section 7-178.

Neon tube indicator devices 16-166 are used to indicate the presence ofpulses at transformer 16-167. A capacitive coupling member 16-168outside the tube envelope permits pulsating energy to discharge the tubeand provide a visual indication useful in servicing throughout thecomputer system. This device is described in United States Patent No.2,970,303, issued Jan. 31, 1961, to Robert J. Williams, for Neon LampIndicator Device, and assigned to the same assignee the presentapplication.

The recording of information upon the magnetic drum is in generalaccomplished with the same magnetic transducer heads as used for readingby means of circuits described in FIGS. 17 through 19. The basicinformation to be written upon the drum is derived at input terminals M,N, T, etc. of the logical "and circuits 17-163 of FIG. 17 and are timedby means of the w drum writing pulses at the input terminal U of thediode and circuits 17-163. Thus, a pulse is derived at the outputtransformer 17-180 of the amplifier tube 17-182 which has a duration ofone and one-half microseconds, and which is used in the output datawriting circuits at terminals F, H, S, etc., for the respective threedrum channels which comprise the B register or multipiication-divisionwrite circuit, the data write circuit, and the accumulator or loop writecircuit. Throughout the writing channels, return to negative magneticrecording techniques are utilized. Thus, the circuits are designed toseparately write digital information in the form of both 1 and digits.Each writing preamplifier 17-182 comprises a half of a 6211 typeduotriode. By means of selected input signals, each duo-triode tube isdesigned to write only one of the signals 0 0r 1 necessary for writing abit of information on the drum. In this manner, when writing, one-halfof each triode is conducting each time one of the drum writing pulses woccurs. The circuits are designed to operate at a continuous drumwriting frequency of 1,300 pulses per drum revolution so that a seriesof either 0 or 1 data signals may be recorded.

The actual drum writing circuits by which the output signals ofpre-amplifiers 17-182 are coupled to the magnetic writing heads areshown in FIG. 18. The drum readwrite circuits are shown for the threeseparate data sections of the magnetic drum. These sections, namely thememory or data tracks, the A register loop and the B register track eachhave provisions for reading and writ ing magnetic information upon thedrum. In each of the three data sections similar read and writeamplifiers are utilized for Writing alternatively Is and Os as specifiedby output signals from the circuits shown in FIG. 17b. Each 0 thewriting amplifiers 18-184 comprises a 6216 type pcntode tube, which iscoupled to one-half of a magnetic transducer head winding 18-186. Bycenter tapping the winding 186 of the magnetic head and driving it atopposite ends with separate amplifier tubes, 1 and O signals may bewritten upon the drum alternatively.

Since the A register circuit comprises a circulating loop for re-entryof information upon the same memory track after suitable modification, aseparate reading head is spaced at fixed distance of about one computerword from the loop writing head 188. However, in the B register andmemory sections the same magnetic head winding is used both as a readingand writing head. In order to couple the signal to succeeding amplifiercircuits from the single magnetic head, a read amplifier transformer18-190 is coupled with its primary winding in shunt with the magnetichead windings 18-186.

A single head is coupled with each magnetic drum track, with theexception of the A register track which is coupled for re-entry ofinformation. Separate reading and writing heads are provided for the Aregister loop. In the memory section there are ten data tracks 0 through9, each of which may be individually selected so that reading andwriting may be accomplished upon only one track at a time. Thus, asingle read and write circuit is provided for the entire memory section.The particular memory track is selected by setting up the switch section18-192 by means of address selection instructions from either thehereinbefore described pinboard 3- 6 or the manual control panel 3-48.The tens level digit 0-9 of the selected instructions, for example, mayoperate a channel selector relay 18-194 individual to the magnetic headof each track in order to operate the associated single poledoublc throwswitch contact. Only one switch contact, such as 18-196, is connected tothe +210 v. terminal 200 at a time, therefore permitting the selectionof only one track such as the 0 track shown in the drawing.

in this selection scheme, each memory section reading head 18-188 hasits associated winding 18-186 coupled to two opposite buses 13-197 and18-198 by means of poled unidirectional devices such as the illustrateddiodes. A cutoll bias is supplied to these diodes by way of theunselected windings of tracks 1 through 9 which apply to the respectivehead winding center tap terminals the +195 volts available at the powersupply terminal 18-199. This supplies to the unselected diode anodes apotential of about 15 volts negative with respect to the +210 voltsavailable at power supply terminal 18-200 which is coupled to buses 197and 198 through the winding of the 0 track head selected by switchcontact 196. Thus, each of the diodes of the non-selected heads presentsmaximum reverse impedance so that little current flows therethrough.Accordingly, potentials which are generated in the non-selected windingswith signals presented by rotation of the drum are not transferred tobuses 197 and 198 where they may be seen by the reading amplifiertransformer winding 191, nor will conduction of one of the memory writeamplifiers 184 cause current to flow in any unselected winding toproduce undesired writing upon the drum. However, when the input signalsare applied to one of the write amplifiers 18-1, electron current iscaused to flow from the volt amplifier cathode potential through therespective amplifier tube 184 and the corresponding section of theselected reading winding 186 to the switch contact 196 and back throughthe +210 volt power supply terminal 200. In this manner, a singleread-write amplifier circuit may serve for a plurality of memory datachannels in the computer system. This circuit is described and claimedin United States Patent No. 2,932,008, issued Apr. 5, 1960, of George G.Hoberg, for Matrix System, and assigned to the same assignee as thepresent application.

In order to read from the plurality of memory channels, the readamplifier primary winding 191 is coupled to :1 +195 volt power supplyterminal 199. This assures 75 a current flow from the +210 volts at thecenter tap of

2. IN AN ELECTRONIC DIGITAL COMPUTER SYSTEM, A SOURCE OF CYCLICALLYPRESENTED SYNCHRONIZING SIGNALS HAVING A PLURALITY OF CHANNELS, AT LEASTONE MEANS IN THE SOURCE FOR PRESENTING AT A SINGLE SIGNAL CHANNEL APLURALITY OF INTERMIXED SETS OF SYNCHRONIZING SIGNALS FOR CONTROL OFDIFFERENT COMPUTER CIRCUITS, AT LEAST ONE OTHER MEANS IN THE SIGNALSOURCE FOR PRESENTING A FURTHER SET OF SYNCHRONIZING SIGNALS AT ANOTHERCHANNEL FOR USE IN THE COMPUTER CIRCUITS AND HAVING A SYNCHRONOUSLYTIMED RELATIONSHIP WITH ONE OF THE INTERMIXED SETS OF SIGNALS, A CIRCUITCOUPLED TO SAID SIGNAL CHANNEL FOR AMPLIFYING AND SHAPING THE INTERMIXEDSETS OF SIGNALS, A CIRCUIT COUPLED TO THE OTHER MEANS FOR AMPLIFYING ANDSHAPING THE FURTHER SET OF SYNCHRONIZING SIGNALS, AND COINCIDENCE GATINGMEANS COUPLED TO SAID CIRCUITS FOR COMPARING THE TWO SETS OF AMPLI-